1364.1-2002 IEEE Standard for Verilog Register Transfer by PDF

ISBN-10: 0738135011

ISBN-13: 9780738135014

Common syntax and semantics for VerilogR HDL-based RTL synthesis are defined during this usual.

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Extra info for 1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis

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6 Arithmetic expressions with regs and integers Supported. 7 Relational operators Supported. == shall not be supported. 9 Logical operators Supported. 10 Bit-wise operators Supported. 11 Reduction operators Supported. 12 Shift operators Supported. Copyright © 2002 IEEE. All rights reserved. 13 Conditional operator Supported. 14 Concatenations Supported. 15 Event or Supported. 1 Vector bit-select and part-select addressing Supported. 2 Array and memory addressing Supported. 3 Strings Supported. 3 Minimum, typical, and maximum delay expressions constant_expression ::= constant_primary | unary_operator { attribute_instance } constant_primary | constant_expression binary_operator { attribute_instance } constant_expression | constant_expression ?

2 Returning a value from a function Supported. 3 Calling a function function_call ::= hierarchical_function_identifier { attribute_instance } ( expression { , expression } ) Recursion with a static bound shall be supported. 4 Function rules Supported. 5 Use of constant functions Supported. 9 Disabling of named blocks and tasks disable_statement ::= disable hierarchical_task_identifier ; | disable hierarchical_block_identifier ; The block identifier shall be that of the enclosing block. Disable of any other blocks shall not be supported.

NOTE—Definitions: Set logic—the logic that sets the output of storage device to 1; reset logic—the logic that sets the output of storage device to 0. When no signal names are specified in the attribute instance, both set and reset logic signals shall be applied directly to the set/reset terminals of a level-sensitive storage device. When signal names are specified, only the specified signals shall be connected to the set/reset terminals (others are connected through the data input of the level-sensitive storage device).

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1364.1-2002 IEEE Standard for Verilog Register Transfer Level Synthesis

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